1. Field of the Invention
The present invention relates to a pattern generator employed in a memory test apparatus.
2. Description of the Related Art
As a main storage device for an electronic computer such as a personal computer, a workstation, etc., DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) is employed.
In a case of testing memory, data is written to a cell in the memory, following which the data thus written is read out, and judgment is made whether or not the data thus read out matches an expected value. Thus, such an arrangement judges the quality of the overall operation of the memory, or identifies a defective cell. Such a test apparatus includes, as an internal circuit, an address signal generating circuit configured to generate an address signal that indicates the address of a cell to be accessed. The test apparatus uses the address signal generated by the address signal generating circuit to read/write data.
In some cases, in order to test the memory in a state near that of actual use, i.e., in a random access manner, the address to be accessed is changed according to a predetermined pattern. In order to provide such a function, in some cases, the test apparatus mounts an address inverting circuit configured to invert all the bits of the address generated according to the pattern program. By employing such an address inverting circuit, such an arrangement is capable of changing the position of the memory cell to be accessed in a simple manner.
Related Patent Documents
Japanese Patent Application Laid Open No. 2000-123597 International Publication WO 2004/113941 pamphlet
However, in recent years, memory has a burst transmission function. An address that is used in performing burst transmission, i.e., in general, the lower several bits of a column address, should not be inverted. If such an address is inverted, a cell to be accessed is not accessed.